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MOS INTEGRATED CIRCUIT
PD16310
HIGH VOLTAGE CMOS DRIVER FOR PDP, EL, VFD
DESCRIPTION
PD16310 is high voltage driver for PDP, EL or VFD graphic panel structured by CMOS process. Logic power
supply is 5.0 V connecting direct to control logic. Maximum output voltage is 80 V and maximum current is 50 mA.
FEATURES
* 80 V Output Voltage Swing Capability * 50 mA Output Sink and Source Current Capability * 40 bit Shift-register and Latch * High Speed Serial DATA Transferring (fmax. = 20 MHz * Low Standby Current 100 A
MIN.)
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (3 direction lead)
PD16310GF-3L9
Document No. IC-2859 (1st edition) Date Published March 1997 P Printed in Japan
(c)
1993
PD16310
PIN CONNECTION DIAGRAM (Top View)
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 VDD2 VSS2 VSS2 VSS1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 VDD2 VSS2 VSS2 VSS1
R/L
VDD1
PC
NC
NC
A
CLK
NC
NC
NC
B
STB
BLK
NC
VDD1
Note The 33 pin (NC) should be open. All the power supply terminals should be used. VSS1 and VSS2 should be respectively connected with themselves outside. To prevent latch up breakdown, the power should be turned ON in order VDD1, logic input, VDD2. It should be turned OFF in the opposite order. This relationship should be followed during transition period as well.
2
NC
PD16310
BLOCK DIAGRAM
PC BLK STB O1 L1
S1 A A
STB
CLK
CLK
R/L
R/L
B
B S40 L40
*
O40
40 bit Shift Register
40 bit Latch
* High Voltage CMOS Driver 80 V 50 mAMAX.
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PD16310
PN CONFIGURATION
PIN No. 27 37 36 30 SYMBOL PC BLK STB A PIN NAME Polarity Change Input Blank Input Latch Strobe Input Right Data Input/Output FUNCTION All driver outputs' level are inverted while PC is L. All driver outputs are H or L while BLK is H. Latch's status is data through while STB is L. R/L = H : A = IN, B = OUT R/L = L : A = OUT, B = IN
35 31
B CLK
Left Data Input/Output Clock Input Data of shift-register is shifted while CLK is going H to L. (Negative edge is active.) H: Right Shift Mode A O1 *** O40 B L: left Shift Mode B O40 *** O1 A High voltage output 80 V, 50 mA 5.0 V 10 % 10 to 70 V Connect to the system ground. Connect to the system ground. No. 33 pin should be open.
25
R/L
Shift Direction Control Input
1 - 20 45 - 64 26, 39 21, 44 24, 41 22, 23, 42, 43 28, 29, 32 - 34 38, 40
O1 - O40
Driver Outputs
VDD1 VDD2 VSS1 VSS2 NC
Logic Power Supply Driver Power Supply Ground (for Logic) Ground (for Driver) No Connect
TRUTH TABLE 1 (Shift-Register part)
INPUT R/L H H L L CLK H or L H or L A IN IN OUT OUT IN/OUT SHIFT-REGISTER B OUT OUT IN IN DATA is shifted. No Change. DATA is shifted. No Change.
TRUTH TABLE 2 (Latch, Driver part)
INPUT DRIVER OUTPUT A (B) X X H H L L X X STB X X L L L L H H BLK H H L L L L L L PC H L H L H L H L ALL H ALL L H L L H Latch's data output Latch's data output (inverting)
X = H or L, H = High Level, L = Low Level
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PD16310
TIMING CHART
( A (B) (INPUT) ) : R/L = L
CLK
S1 (S40)
S2 (S39)
S3 (S38)
STB
BLK
PC
O1 (O40)
O2 (O39)
O3 (O38)
5
PD16310
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C, VSS1 = VSS2 = 0 V)
PARAMETER Logic Power Supply Input Voltage Logic Output Voltage Driver Power Supply Driver Output Voltage Drive Maximum Current Power Dissipation Operating Temperature Storage Temperature SYMBOL VDD1 VI VO1 VDD2 VO2 IO2 PD Topt Tstg RATINGS -0.5 to +7.0 -0.5 to VDD1 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to 80 -0.5 to VDD2 + 0.5 50 1 000 -40 to +85 -65 to +150 UNIT V V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS (Ta = 25 C, VSS1 = VSS2 = 0 V)
PARAMETER Logic Power Supply High Level Input Voltage Low Level Input Voltage Driver Power Supply Driver Output Current SYMBOL VDD1 VIH VIL VDD2 IOL2 IOH2 MIN. 4.5 0.7 * VDD1 0 10 TYP. 5.0 MAX. 5.5 VDD1 0.2 * VDD1 70 +40 -40 UNIT V V V V mA mA
DC CHARACTERISTICS (Ta = 25 C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V)
PARAMETER Hight Level Output Voltage Low Level Output Voltage High Level Output Voltage SYMBOL VOH1 VOL1 VOH21 VOH22 Low Level Output Voltage VOL21 VOL22 High Level Input Current Low Level Input Current High Level Input Voltage Low Level Input Voltage Standby Current IIH IIL VIH VIL IDD1 IDD1 IDD2 IDD2 0.7 * VDD1 0.2 * VDD1 10 100 100 1 000 69 65 1.0 10 1.0 -1.0 MIN. 0.9 * VDD1 0.1 * VDD1 TYP. MAX. UNIT V V V V V V TEST CONDITIONS Logic, IOH1 = -1.0 mA Logic, IOL1 = 1.0 mA O1 - O40, IOH2 = -1.0 mA O1 - O40, IOH2 = -10 mA O1 - O40, IOL2 = 5.0 mA O1 - O40, IOL2 = 40 mA VI = VDD1 VI = 0 V
A A
V V
A A A A
for VDD1, Ta = 25 C for VDD1, Ta = -40 to +85 C for VDD2, Ta = 25 C for VDD2, Ta = -40 to +85 C
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PD16310
AC CHARACTERISTICS (Ta = 25 C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF)
PARAMETER Delay Time SYMBOL tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHL5 tPLH5 Rise Time Fall Time Maximum Frequency Input Capacitance tTLH tTHL fmax. CI 20 30 10 20 MIN. TYP. MAX. 50 50 160 160 150 150 145 145 140 140 70 70 UNIT ns ns ns ns ns ns ns ns ns ns ns ns MHz pF O1 - O40 O1 - O40 Duty = 50 %, for CLK PC O1 - O40 BLK O1 - O40 STB O1 - O40 CLK O1 - O40 TEST CONDITIONS CLK A/B
AC TIMING REQUIREMENT (Ta = -40 to +85 C, VDD1 = 4.5 to 5.5 V, VDD2 = 10 to 70 V VSS1 = VSS2 = 0 V)
PARAMETER Clock Pulse Width Strobe Pulse Width Blank Pulse Width Polarity Change Pulse Width Data Setup Time Data Hold Time Setup Time SYMBOL PWCLK PWSTB PWBLK PWPC tSETUP tHOLD tCLK-STB MIN. 20 20 200 200 10 10 50 TYP. MAX. UNIT ns ns ns ns ns ns ns for CLK to STB TEST CONDITIONS
7
PD16310
AC CHARACTERISTICS WAVEFORM
1/fCLK PWCLK(L) PWCLK(H) VDD1 CLK 50 % 50 % 50 % VSS1 tSETUP tHOLD VDD1 A/B (INPUT) 50 % 50 % 50 % VSS1 tPHL1 tPLH1 VOH1 B/A (OUTPUT) tPHL2 50 % 50 % VOL1 tTHL VOH2 90 % On 10 % 10 % tPLH2 tTLH VOL2 90 %
VDD1 CLK 50 % VSS1 tCLK-STB PWSTB VDD1 STB 50 % 50 % VSS1 tPHL3 VOH2 90 % On VOL2 tPLH3 On 10 % VOL2 VOH2
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PD16310
PWBLK BLK 50 % 50 % VSS1 tPHL4 90 % On 10 % VOL2 tPLH4 VOH1 VDD1
PWPC VDD1 PC 50 % 50 % VSS1 tPHL5 90 % On 10 % VOL2 tPLH5 VOH2
9
PD16310
PACKAGE DIMENSIONS
80 PIN PLASTIC QFP (THREE DIRECTIONS) (14x20)
A B
64 65
41 40
detail of lead end
CD
S Q F R
80 1
25 24
G H P I
M
J
K M N L
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.30.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX.
INCHES 0.8780.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P80GF-80-3L9-2
10
PD16310
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions.
PD16310GF-3L9
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 230 C or below, Reflow time: 30 seconds or below (210 C or higher), Number of reflow process: 1, Exposure limit*: None Peak package's surface temperature: 215 C or below, Reflow time: 40 seconds or below (200 C or higher), Number of reflow process: 1, Exposure limit*: None Terminal temperature: 300 C or below, Flow time: 10 seconds or below, Exposure limit*: None Symbol IR30-00-1
VPS
VP15-00-1
Partial heating method
* Exposure limit before soldering after dry-pack package is opened. Storage coditions: 25 C and relative humidity at 65 % or less. Note Do not apply more than a single process at once, except for "Partial heating method."
11
PD16310
[MEMO]
12
PD16310
[MEMO]
13
PD16310
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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